In recent decades, the ever increasing data-updating speed stimulates the demands not only on storage capacity of random access memories (RAMs), but also on the writing speed thereof.
Conventional RAMs mainly include Flash Memories, Resistive RAMs (ReRAMs), Phase Change RAMs (PCRAMs), and Ferroelectric RAMs (FeRAMs), etc. Memory cells in the aforesaid RAMs usually adopt a so-called two-terminal approach (i.e., to have both a bit line and a write line) for data transmission, and may be implemented into multilevel structures to reduce their sizes and to accordingly increase an areal density. However, such conventional RAMs require an initialization procedure prior to their data writing-in writing/rewriting process, the memory cells need to be initialized into a low resistance state (LRS), and such initialization procedure is energy and time consuming.
On the other hand, due to the discovery of tunneling magnetoresistance (TMR), Magnetic Random Access Memories (MRAMs) composed of a magnetic free layer, an insulating barrier layer and a ferromagnetic pin layer have come into play in recent years and are deemed as a promising next generation memory technology. Such MRAMs have their logic levels, e.g., 0 and 1, determined by manipulating magnetic moments of the free layer via electron spinning under applied currents and external magnetic fields, such that the resistance of memory cells can be altered accordingly. Conventional MRAMs include spin-transfer torque magnetic random access memories (STT-MRAMs) and spin-orbit torque magnetic random access memories (SOT-MRAMs).
Referring to FIG. 1, Yiming Huai et al. discloses a conventional STT-MRAM 1 in “Spin-Transfer Torque MRAM (STT-MRAM): Challenges and Prospects”, AAPPS Bulletin December 2008, Vol. 18, No. 6, pp. 33 to 40 (hereinafter Reference 1), including a silicon substrate 11 having a transistor 111 formed thereon, an STT memory cell 12 (i.e., a magnetic tunnel junction (MTJ)) electrically coupled to and disposed on the transistor 111, and a bit line 13 disposed on the STT memory cell 12. The STT memory cell 12 includes a free layer 121 electrically connected to the bit line 13, a pin layer 122 electrically connected to the transistor 111, and an MgO tunnel barrier layer 123 disposed between the free layer 121 and the pin layer 122. The transistor 111 serves as a word line for reading and writing data from the STT memory cell 12. However, during the write-in operation of the conventional STT-MRAM 1, a relatively high writing voltage (current) is applied across the STT memory cell 12, which may damage the free layer 121, as well as the MgO tunnel barrier layer 123, and result in reliability issues such as time-dependent dielectric breakdown.
Referring to FIG. 2, Yusung Kim et al. discloses a conventional SOT-MRAM 2 in “Multilevel Spin-Orbit Torque MRAMs”, IEEE Transactions on Electron Devices, Vol. 62, No. 2, February 2015 (hereinafter Reference 2), which may solve the aforesaid issue for the conventional STT-MRAMs. The conventional SOT-MRAM 2 includes an SOT memory cell 21 (i.e., the magnetic tunnel junction) and a heavy metal layer 22. The SOT memory cell 21 has a free layer 211, a pin layer 212, and a tunnel barrier layer 213. The heavy metal layer 22 electrically contacts the free layer 211 and is electrically connected to a write-in bit line 23. The pin layer 212 is electrically connected to a read bit line 24, where the write-in bit line 23 is arranged interlacingly with the read bit line 24 and a bit line 25, so as to constitute a three-terminal configuration for signal transmission. Writing of such conventional SOT-MRAM 2 can be realized by injecting the spin current, which is generated from spin-orbit interaction caused by the current flowing in the heavy metal layer 22, into the free layer 211 so as to reverse the magnetic moments of the free layer 211. However, the occupied volume of such SOT memory cell 21 is relatively large due to the three-terminal configuration, and the areal cell density of the same may thus be relatively low.
In order to solve such issue, Kim et al. discloses another SOT-MRAM 3 in Reference 2 as illustrated in FIGS. 3 and 4, where the memory cells thereof include a first SOT cell 31 (i.e., the mtj), a second SOT cell 32 and a heavy metal layer 33, where the first and second SOT cells 31, 32 are connected in series (see FIG. 3) or in parallel (see FIG. 4) so as to create four resistive states and to achieve multilevel storage. However, such multilevel storage is achieved by increasing the number of the SOT cells 31, 32, which may still result in a relatively large occupied volume of the SOT-MRAM 3 and would not be able to increase the areal density of the memory cells.